发明名称 Control system for interruption long data transfers between a disk unit or disk coche and main memory to execute input/output instructions
摘要 A control system for a disk cache memory is disposed between a main memory unit and a disk unit for storing a record of data from the disk unit. The control system is designed such that when an input/output instruction is issued from a CPU while data loading is being performed from the disk unit to the cache memory, it interrupts the data loading once so that an input/output instruction from the CPU can be executed, thereby considerably reducing the time of wait for execution of the input/output instruction.
申请公布号 US4819203(A) 申请公布日期 1989.04.04
申请号 US19870038704 申请日期 1987.04.15
申请人 HITACHI, LTD. 发明人 SHIROYANAGI, YOSHIRO;KURANO, AKIRA
分类号 G06F12/08;(IPC1-7):G06F9/00;G06F13/00;G06F13/26 主分类号 G06F12/08
代理机构 代理人
主权项
地址