发明名称 |
High speed non-return-to-zero digital clock recovery apparatus |
摘要 |
A digital clock recovery circuit is presented which uses a delay line to produce a plurality of delayed sample signals. The sample signals are used to sample incoming data in a phase detector and the resultant sampled data is then resampled by the tentatively correct apparatus clock output signal. The resampled data provides a direct indication of the phase difference beween the data and the clock and the value can be obtained using a summing circuit. If the summed amount is outside an allowable range of values, a phase altering signal is supplied to an oscillator to change the phase of the apparatus clock output signal.
|
申请公布号 |
US4819251(A) |
申请公布日期 |
1989.04.04 |
申请号 |
US19880190913 |
申请日期 |
1988.05.06 |
申请人 |
ROCKWELL INTERNATIONAL CORPORATION |
发明人 |
NELSON, BLAINE J. |
分类号 |
H03L7/081;H04L7/033;(IPC1-7):H03L7/00 |
主分类号 |
H03L7/081 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|