发明名称 TELEVISION RECEIVER
摘要 PURPOSE:To reduce the rolling or the skew of a picture by constituting a clock generation circuit and a horizontal deflection circuit in one PLL circuit. CONSTITUTION:A video signal from an input terminal 13 is separated into a luminance signal and a chrominance signal by a comb line filter 14, and further, the chrominance signal is inputted to a digital signal processing circuit through A/D converters 16 respectively, after it is demodulated by a chrominance demodulator 15. A synchronizing system is provided with the clock generation circuit 11, whose input is a horizontal synchronizing signal from a synchronizing separation circuit 22. The clock generation circuit 11 and the horizontal deflection circuit 2, including a horizontal output circuit 7 and a flyback transformer 8, constitute one PLL circuit.
申请公布号 JPS6489683(A) 申请公布日期 1989.04.04
申请号 JP19870243736 申请日期 1987.09.30
申请人 HITACHI LTD;HITACHI VIDEO ENG CO LTD 发明人 SEKIYA HIROSHI;ARAI IKUYA;MURATA TOSHINORI
分类号 H04N5/04;H04N5/12;H04N5/44 主分类号 H04N5/04
代理机构 代理人
主权项
地址