| 摘要 |
PURPOSE:To erase some of the memory cells along a word line with reliability and no risk of erroneous writing by providing erase lines, which are narrower than source lines, on the source lines coated with oxide film. CONSTITUTION:Erase lines 29 and 30 are laid in parallel with word lines 26, 27 and 28, and perpendicular to bit lines 22 and 23. The erase lines 29 and 30 are narrower than a source region in a memory cell array, and laid over source lines but not over a field oxide. When a high voltage is applied to one erase line 30 alone with the other erase line 29 grounded, only the transistors Tr21, Tr22, Tr31 and Tr32 are erased along the erase line 30. The transistors Tr11 and Tr12 in erase inhibit state will never be written erroneously because their control gates, erase gates, source regions, and drain regions are all grounded. |
