DEMODULATED CLOCK REPRODUCING CIRCUIT

摘要

PURPOSE:To reduce a circuit scale by providing a deciding means to decide which burst signal is supplied, at present, to the phase comparing means of a PLL circuit to reproduce a clock for demodulation, and driving the PLL circuit alternatively with a color burst signal and a burst signal for highly fine information demodulation according to a decided output. CONSTITUTION:An Sfssc/Sfc deciding circuit 520 of burst signals Sfc and Sfc decides whether the burst signal inputted in a phase comparator 503 at present is a color burst signal Sfsc or a burst signal Sfc for highly fine information demodulation. A selector circuit 512 alternatively supplies the input signal to either of a latch circuit 513 for the Sfsc or a latch circuit 514 for the Sfc by the selector circuit 523 in accordance with the decision result of the deciding circuit 520. Thus, the clocks of frequencies fsc and fc of the said two burst signals are outputted from respective variable oscillators 515 and 516. An output terminal 521 obtains the clock for the chrominance signal demodulation, and an output terminal 522 obtains the clock for the highly fine information demodulation.