| 摘要 |
PURPOSE:To reduce the number of each functional element in a logic circuit constituting a register by providing a capacitor between a first and a second switching elements, accumulating an inputted signal there and successively transmitting it to a first and a second inverters. CONSTITUTION:The inputted signal VIN from a front stage shift register which is not shown by a figure is inputted to an input terminal 11. To this input terminal 11, the drain D of the N channel MOS 12 of the first switching element is connected and the drain D of the N channel MOS 13 of the second switching element is connected to a source S. Between the MOSs 12 and 13, the capacitor 14 where one end is grounded is provided and shift pulses A and B are respectively impressed on the gates of the MOSs 12 and 13. To the back stage of the MOS 13, the first inverter 15 consisting of MOSs 15-1 and 15-2 and the second inverter 16 consisting of MOSs 16-1 and 16-2 are provided in series, the MOSs 15-2 and 16-2 are successively operated by using charge accumulated in the capacitor 14 and the MOSs 15 and 16 including them are successively outputted. |
