| 摘要 |
<p>PURPOSE:To enlarge a noise margin at the time of normal reading by setting a data detection reference more strictly at the time of verifying than that at the time of the normal reading. CONSTITUTION:At the time of the verifying and at the time of the normal reading, the ON/OFF state of a transistor for switching is switched and the number of a load transistor or the number of the load transistor of a bit line at a dummy cell side or the number of a transistor in a data detection circuit is switched to the dummy cell side. Thus, the data detection reference can be set more strictly at the time of the verifying than that at the normal reading and the difference between a read potential and a reference potential is enlarged at the time of the normal reading after passing a verifying check. So that, a column selection transistor 2 and the load transistor 4 are connected in series to an EPROM 1 and the dummy cell 1, a selection transistor 2 and a load transistor 4 which are connected in series are provided on the joint of the transistors 2 and 4. Besides, a high voltage detection circuit 6 is provided.</p> |
