APPARATUS AND METHOD FOR GENERATING DATA INDUCTION STATE SIGNAL

摘要

PURPOSE: To accelerate the execution speed by executing an instruction causing an error state signal when a pool value representing the validity of the operation is stored in a prescribed address of a prescribed scalar register. CONSTITUTION: Before the execution of a low bit error clear (FLBC) instruction, a pool value as a result of comparison arithmetic operation is generated. The comparison arithmetic operation sets or clears low-order bits in a designated scalar register depending on the validity of the comparison arithmetic operation. In the FLBC instruction, a prescribed register is tested and when an erroneous pool value stored therein is found out, the presence of the error state generates a signal in an error control program. The FLBC instruction (since no branch for sub routine call is provided) quickens the execution time and a few program codes requiring for the operation are enough.