发明名称 VERTICAL MOS TRANSISTOR
摘要 PURPOSE:To prevent the variation in threshold voltage and the degradation of gm by preparing a second electrode buried in a second groove coated with gate insulation and a third electrode which is formed on at least one side of an opening in the second groove and forms a second rectifying junction in cooperation with a semiconductor substrate. CONSTITUTION:At the bottom of a groove 9, an n<+> polysilicon 3 and a substrate 1 are in contact to form an n<+> layer 2 on the substrate. The electrode groove 9 is adjacent to a gate groove 10 in which a polysilicon gate electrode 6 is buried. The gate groove 10 is connected to an n<+> polysilicon 8. A p-n junction is formed between the n<+> polysilicon 8 and a substrate 1 by diffusion from the polisilicon 8 and the substrate. The n<+> layer 2 serves as a source-drain region. For external connection of the n<+> polysilicon 3, the electrode groove 9 is extended outside the MOSFET and connected to an interconnection layer on a surface oxide layer through an opening provided in the surface oxide layer.
申请公布号 JPS6486561(A) 申请公布日期 1989.03.31
申请号 JP19880116592 申请日期 1988.05.13
申请人 NEC CORP 发明人 MIKOSHIBA KEIMEI
分类号 H01L27/10;H01L21/8242;H01L27/108;H01L29/78 主分类号 H01L27/10
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