Circuit arrangement for controlling reset commands in digitally controlled communications systems

摘要

The invention relates to a circuit arrangement for controlling reset commands in digitally controlled communications systems, especially for decentralised input/output processors controlling peripherals. "Reset common" (SRG) or "reset individual" (RSI) signals produced by the shift register device (SRG) are fed to the counting device (ZAE) and are fed from there to the reset line output (RSL) in a time-delayed manner as a "reset" (RS) signal, as a function of the signal which is in each case still present. The control of reset commands is carried out in digitally controlled communications systems. <IMAGE>