发明名称 GATE ARRAY INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF
摘要 <p>PURPOSE:To realize a plurality of dissimilar memories by a method wherein memory cells capable of modifying the function of each memory are arranged in the form of matrix and address input signal buffer circuits and decoder circuits, which are used for selecting these memory cells, are prepared in advance a plurality of pieces. CONSTITUTION:A basic array region BCA and a region MA for a memory's exclusive use having a memory matrix MRA consisting of RAMs and a memory matrix MRO consisting of ROMs are provided. Moreover, the region for a memory's exclusive use is independently provided with the MRA consisting of address input signal buffer circuits ABRA and ABRO, word decoders DRA and DRO, an input/output circuit DIO and an output circuit DO and an attachment circuit related to the MRO. The respective memories are actuated independently. Thereby, two groups of dissimilar and independent memories can be made by forming dividedly a word line within the memory matrix(MA) at a part shown by a one dotted chain line according to customers' wishes.</p>
申请公布号 JPS6484635(A) 申请公布日期 1989.03.29
申请号 JP19870240671 申请日期 1987.09.28
申请人 MATSUSHITA ELECTRON CORP 发明人 KATAOKA MASAHIRO
分类号 G11C11/41;G11C11/401;H01L21/82;H01L21/822;H01L27/04;H01L27/10;H01L27/118 主分类号 G11C11/41
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