| 摘要 |
PURPOSE:To improve processing ability by separating the bus of a microprocessor from a bus for packet transmission and reception and also separating the memory of the microprocessor and a packet buffer memory. CONSTITUTION:Individual receiving FIFOs 51-5n put data into packets, which are transferred to a triple-port memory 9, one by one, and sent out to a multiplex line 15 after their headers are rewritten in headers for the multiplex line. Then the packets which are received from the multiplex line 14 and separated have the headers rewritten in headers for individual communication lines by the triple-port memory 9 and are sent in the packet form to individual transmitting FIFOs 61-6n indicated by the headers. Consequently, a microprocessor 11 is not used exclusively for the header rewriting to interrupt its operation every time a packet is received, and any overrun due to the delayed handling of a reception request is not caused; and individual communication lines 1 and 2 can transfer data in packets through the data transfer bus 7 and the packet demultiplexing ability is improved.
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