| 摘要 |
PURPOSE:To make the phase comparison output characteristic symmetrical independently of the pulse width of an input signal by accepting only the leading of a data signal for a period of a gate signal representing the phase comparison enable range. CONSTITUTION:A gate signal generating section 9 generates a gate signal existing for a period corresponding to the period of the clock from the production of one edge of the clock CK. A 1st flip-flop 10 reaches one state at one edge of an edge data input (b) in the presence of the gate signal. The output of the flip-flop 10 is stored by a 2nd flip-flop 3 acted at one edge of the said clock CK. When a 2nd flip-flop 3 reaches one state, the 1st flip-flop 10 is brought into the other state to output the output of the 1st flip-flop as a signal corresponding to the phase difference information between the edge input (b) and the clock CK. |
