发明名称 PROGRAMMABLE LOGIC DEVICE
摘要 PURPOSE:To use a signal line effectively and to decrease the number of signal lines forming the bus line by providing the bus line where lots of kinds of signals coexist in time division through the detection of the address between at least two or over of programmable circuits. CONSTITUTION:An n-bit data bus 5, an m-bit control address bus 6 and a clock line 7 are arranged to a bus line region 4, and bus lines 5-7 are connected to all or a prescribed part of the programmable circuit 1. The programmable circuit 1 being a caller uses a proper means such as monitor of a specific bit to monitor an idle bus line and the address specific to the other programmable circuit 1 at the receiver side desiring to transmit/receive the data is sent to a control/address bus 6. When the transmission/reception of data is finished, floating state, for example, is attained to release the bus line thereby allowing other programmable circuit 1 to use the bus line.
申请公布号 JPS6480128(A) 申请公布日期 1989.03.27
申请号 JP19870238160 申请日期 1987.09.22
申请人 KAWASAKI STEEL CORP 发明人 KAWANA KEIICHI
分类号 G06F7/00;H03K19/173;H03K19/177 主分类号 G06F7/00
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