| 摘要 |
PURPOSE:To improve integration of building block system chips and shorten designing period by optimizing Boolean expression of logic block, calculating and comparing the area and characteristics of logic block for each case of PLA and standard cell/. and performing generation processing, automatically selecting an advantageous system. CONSTITUTION:After the start, the Boolean expression of a logic circuit block 2 is read. Then, the pool expression is optimized. And the area and characteristics of a logic circuit block 3 which was realized as PLA is calculated. The area and characteristics of a logic circuit block 4 where the input Boolern expression was realized as a standard cell 1 are calculated. The cases of the PLA and standard cell 1 are compared in terms of area and characteristics. This selected system allows logic circuit blocks to be generated automatically. Thus, internal logic circuit blocks can be effectively and automatically generated in the hierarchical LSI automatic layout. |
