| 摘要 |
PURPOSE:To prevent the generation of a soft error in a memory cell mode by a method wherein, a potential barrier layer is provided under the semiconductor region on the side where it is connected to the information accumulation capacitor of a FET, to be used for memory selection, in a DRAM. CONSTITUTION:A DRAM memory cell M is composed of a memory cell selecting MISFETQs and an information storing capacitor C. A potential barrier layer 4B, which is formed by diffusing impurities and a channel stopper region 4A will be formed thereon, is provided under one semiconductor region 9 located on the side where it is connected to the capacitor C of the above-mentioned FETQs. Also, said channel stopper region 4A and the potential barrier layer 4B are formed in the same manufacturing process. As the minor carrier captured by the above-mentioned information storing capacitor can be reduced through the above-mentioned procedures, the generation of a soft error of a memory cell mode can be prevented, and the number of manufacturing processes can also be reduced. |
