| 摘要 |
PURPOSE:To operate normally even when a clock skew is occurring without enhancing chip area or power consumption by delaying data transmission between latch circuits by a half period of clock. CONSTITUTION:By inserting a p-channel transistor Tr between flip-flops FF1, FF2, the data transmission time from the flip-flop FF1 to the other FF2 can be delayed by 1/2 period of clock. Accordingly, a switch provided between the latch circuits can be made turned off by detecting an edge where a clock signal inputted to the latch circuit in the preceding stage is triggered, and can be made turned on by detecting an edge where said clock signal is not triggered, so that a sufficient delay time can be provided for the inter-latch circuit data transmission. As a result, a shift register that operate normally even at a time of clock skew can be obtained without enhancing chip area or power consumption. |
