| 摘要 |
PURPOSE:To transfer a large quantity of data in a short time without deteriorating the instantaneous response properties of a CPU, by transferring data in a cycle still mode during CPU operation and then separating the CPU from a bus as long as the CPU is not active to transfer data by continuous DMA control. CONSTITUTION:Data is transferred in a cycle still mode as long as a CPU 12 is active when a request is received for transfer of data to be carried out between a memory 13 and an input and/or output device 17 based on the DMA control. While the CPU 12 is separated from a bus 15 in case the CPU 12 is inactive and the data is transferred by the continuous DMA control of a circuit 14. Thus it is possible to improve the efficiency of DMA transfer with the instantaneous response properties secured for the data transfer carried out by the CPU 12 and that carried out by the DMA control. |
