发明名称 EMITTER-COUPLED LOGIC CIRCUIT
摘要 PURPOSE:To accelerate an operation by providing a fourth NPN transistor which discharges electric charge accumulated in the load capacitor of an output terminal. CONSTITUTION:By turning ON first NPN transistors Q1 and Q2, third PNP transistors Q6 and Q7 are turned ON simultaneously, thereby, the fourth NPN transistors Q8 and Q9 are turned ON. Simultaneously with the turning ON of the fourth NPN transistors Q8 and Q9, second NPN transistors Q4 and Q5 are turned OFF. Thereby, the electric charge accumulated in the load capacitors C1 and C2 of the output terminals 13 and 14 are discharged by the fourth NPN transistors Q8 and Q9, and the levels of the output terminals 13 and 14 drops quickly. In such a way, it is possible to accelerate a circuit operation.
申请公布号 JPS6478018(A) 申请公布日期 1989.03.23
申请号 JP19870235866 申请日期 1987.09.18
申请人 FUJITSU LTD 发明人 OMICHI HITOSHI
分类号 H03K19/086;H03K17/04;H03K17/60;H03K19/013 主分类号 H03K19/086
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