| 摘要 |
<p>A multiple element integrated circuit trench cell (10) having at least one vertical field effect transistor (FET) (46) in a wall (17) of a trench (18) in a semiconductor substrate (12). The cell (10) further comprises a central load device (54) within the trench (18) which is electrically connected to the vertical FET (46). The central load device (54) may be an active load device, such as another field effect transistor, or a passive load device, such as a resistor. Additionally, a further FET (50) may be present in another wall (19) of the trench (18) or in a lateral orientation adjacent the trench (18) in the semiconductor surface (14). Two of these multiple element trench cells (10) may be interconnected in various configurations to form conventional static random access memory (SRAM) cells (56).</p> |
