NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE:To enhance an EPROM in reliability by a method wherein coupling capacity is so set as to be smaller between a memory cell floating gate and a substrate than between the floating gate and a control gate for WRITE and ERASE processes may be accomplished dependent solely on the exchange of charges between the floating gate and the substrate so that there will be no large electric field between the control and floating gates and that the oxide film on the floating gate may be protected from deterioration. CONSTITUTION:Control gates 6 of all memory cells are connected respectively to word lines WL1-WL4. Four memory cells M1-M4 are connected in series, with each one of n<+>-type layers 9 to serve as sources or drains being shared by two neighboring memory cells. Selector transistors Q are connected in series to them for the construction of a NAND type cell block. A coupling capacity C1 between a floating gate 4 and a substrate 1 in a memory cell is set at a value that is smaller than a coupling capacity C2 between the floating gate 1 and the control gate 6. Employment of a NAND type cell block of this design for the accomplishment of WRITE and ERASE of data solely through the exchange of electrons between a floating gate and a substrate produces a high- reliability enhanced-integration EPROM.