| 摘要 |
PURPOSE:To obtain a common bus control enabled to shorten one occupation time by releasing the using right of a common bus until the preparation is completed when a data transfer request is detected between two modules connected to the common bus. CONSTITUTION:Common bus using right request lines REQ1-3 are activated when a CPU or an I/O processor IOP requests the using right of the common bus. If any one of CPU or IOP modules request the bus using right, a common bus control device CBC activates common bus using right acknowledge lines ACK1-3 in accordance with priority and informs the activation. When reading operation from the CPU to an external register of the IOP is to be executed, the using right of the common bus is released by a RETRY signal during the preparation of reading data by the IOP. At the writing operation from the CPU to the external register of the IOP, the using right of the common bus is released by a WAIT signal until the completion of the operation. In such constitution one occupation time of the common bus is shortened. |
