发明名称 RESET CONTROLLER
摘要 <p>PURPOSE:To avoid destruction of the memory contents by outputting a reset signal in case a memory interface busy signal is not outputted at the input of a reset request signal and then receiving a forcible reset permission signal for output of the reset signal in case said busy signal kept valid for a fixed time or longer. CONSTITUTION:An external reset request signal and a memory interface busy signal are supplied into a CPU 1 and a reset signal production part 11 produces a reset signal to reset a system. Then the part 11 outputs a reset signal in case no memory interface busy signal is outputted when the reset request signal is received. A forcible reset permission signal is received from a busy signal time monitor part 12 and the reset signal is outputted in case the busy signal is kept valid for a fixed time and longer. In such a way, the destruction of the memory contents can be avoided.</p>
申请公布号 JPS6476306(A) 申请公布日期 1989.03.22
申请号 JP19870235555 申请日期 1987.09.18
申请人 FUJITSU LTD;PFU LTD 发明人 KAWAKATSU MASAHIRO;KATAKURA OSAMU;OKABE KAZUYOSHI;MORIYAMA OSAMU;SUGAWARA HIDEYUKI
分类号 G06F1/24;G06F1/00;G06F12/16 主分类号 G06F1/24
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