发明名称 SENSE AMPLIFYING CIRCUIT FOR READ ONLY MEMORY
摘要 <p>PURPOSE:To shorten an access by executing a conducting only when a bit line electric potential is less than a second value with a second detecting circuit to compare and detect the bit line electric potential with the second value to be lower than a first value and executing the charge with first and second loads. CONSTITUTION:A first detecting circuit 22 detects the electric potential of a bit line 11 and a current to be flown to the bit line 11 is controlled through a current variable circuit 21. Then, for the electric potential of the bit line 11, a first value V1 is held. A second detecting circuit 23 compares and detects the electric potential of the bit line 11 with a second value VTH to be lower than the first value. A switch circuit 24 executes the conducting by the detected output of the second detecting circuit 23 only when the electric potential of the bit line 11 is less than the second value VTH and a current is allowed to flow from a second load 25 to the bit line 11. Thus, the charge up of capacity CS of the bit line 11 is executed with first and second loads 20 and 25 and a charge-up time is shortened. Then, the access time is shortened.</p>
申请公布号 JPS6476498(A) 申请公布日期 1989.03.22
申请号 JP19870231836 申请日期 1987.09.16
申请人 FUJITSU LTD 发明人 RYU YASUSHI
分类号 G11C17/00;G11C16/06 主分类号 G11C17/00
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