| 摘要 |
Individual pieces of digital equipment such as I/O units are provided each with a connect circuit which includes a ROM containing an otherwise incomplete but device-specific, dedicated service program; and each such program portion completes a likewise incomplete program contained in a processor so that this processor can serve as a time-shared controller for each I/O unit. The system includes a common bus, and particular features relate to process inclusion of all ROM's in a common memory continuum.
|
