| 摘要 |
A low 1/f noise amplifier has been provided for an output of a CCD imager. To reduce clock noise, the amplifier employs a differential detection scheme. Linear stages (54, 76) are coupled by capacitors (60, 82) to a differential amplifier (64). Differential amplifier (64) employs a first (112, 118) and a second (172, 198) differential transistor pair. The second differential pair (172, 198) is cross-coupled to the outputs of the first differential pair (112, 118) by load resistances (180, 206) with the voltage drop across them remaining substantially constant. To maintain stability, the positive and negative branches of the amplifier are periodically reset by a resetter (210). The input nodes (62, 86) are periodically reset to a voltage reference.
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