| 摘要 |
<p>PURPOSE:To attain relaying independently of the presence of a logical delay of a relay station by using a reception clock so as to shift the data up tp the input to a FIFO register and using the transmission clock so as to shift the data after the output of the FIFO register. CONSTITUTION:The data up to the input to the FIFO register 11 is shifted by using a reception clock 15 and the data up to a transmission data output terminal 14 from the FIFO register 11 is shifted by using the transmission clock 16 to make the relation of phase of the data pattern and the clock extracted from the data pattern is made always constant. Thus, the accumulation of alignment jitter is eliminated. Thus, when the timing of a data relay system is held, a logical processing section 4 of the selection circuit holds the timing of the data relay system concretely, then the reception data is inputted by the instruction from the logical processing section 4, and when the transmission of the effective information is detected by the logic processing section 4, the transmission data is outputted by an instruction from the logic processing section.</p> |
