| 摘要 |
PURPOSE:To use a CPU allowing a single interrupt as the CPU allowing plural interrupts by performing switching between the output of a priority encoder and an arbitrary address outputted from the CPU in accordance with the output of a vector address decoder. CONSTITUTION:An interrupt request signal generating circuit 16 outputs an interrupt request signal to a CPU 11. A priority encoder 17 gives priority levels to plural interrupts signals and encodes them, and a vector address decoder 18 decodes the vector address which the CPU 11 outputs. A multiplexer 19 performs switching between the output of the encoder 17 and an arbitrary address outputted from the CPU 11 in accordance with the output of the decoder 18, and the switched output of the multiplexer 19 is supplied to a ROM 15 including a vector address area. Then, the address value as the input of the ROM 15 is changed, and contents of this address are outputted to a data bus 14. Thus, the CPU allowing a single interrupt is used as the CPU allowing plural interrupts. |
