| 摘要 |
PURPOSE:To prevent the delay of DMA transfer due to bus lock by giving lower priority for using a bus to a processor, and giving the higher priority for using the bus than the processor to a channel, and permitting the channel to access the bus independently of a bus lock signal. CONSTITUTION:The bus lock signal LOCK is inputted to a priority decision circuit which is provided in each unit and decides a bus use request, but the higher level of the bus use priority is assigned to the channel CHP side, and in addition, the input of the bus lock signal to those is inhibited. Accordingly, even while a system bus is locked between the processors in the lower level, the channel CHP in the higher level of the priority can output the bus use request signal if necessary independently of the bus lock. Accordingly, a bus lock mechanism is valid only among the processors, and the channel CHP is operatable independently of the bus lock. Thus, the deterioration of a system performance due to the delay of the DMA transfer can be prevented. |
