发明名称 CLOCK REPRODUCING USE PLL CIRCUIT
摘要 PURPOSE:To prevent a malfunction by detecting a phase difference only when an edge has existed in an input digital data signal, and controlling a control voltage. CONSTITUTION:When a second detecting edge signal P4 is positioned between a first detecting edge signal P1 and a first delay edge signal P2, or when the second detecting edge signal P4 is positioned between the first delay edge signal P2 and a second delay edge signal P3, a control voltage VC of a voltage control oscillator 12 is controlled. Accordingly, in a blank part of an edge of an input digital data signal Sl, the first detecting edge signal P1 and the first and the second delay edge signals P2, P3 are not outputted, and in this blank part, the control voltage VC of the voltage control oscillator 12 is not controlled but remains as it is. That is, only when the edge has existed in the input digital data signal Sl substantially, a phase difference is detected, and the control voltage VC is controlled. In such a way, a malfunction can be prevented.
申请公布号 JPS6472363(A) 申请公布日期 1989.03.17
申请号 JP19870229146 申请日期 1987.09.11
申请人 SONY CORP 发明人 GOTO HIDEAKI
分类号 G11B20/14;H03L7/08;H03L7/089 主分类号 G11B20/14
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