| 摘要 |
PURPOSE: To improve stability, to enable integration and to unnecessitate adjustment without using any A/D converter by using a circuit provided with a digital type primary phase locked loop(PLL) and a digital secoundary low-pass filter(LPF). CONSTITUTION: A digital type PLL demodulator is formed by combining flip- flops 10 and 12 and a divider module 14 with a state device formed from an exclusive OR (XOR) gate 16, ROM 18 and D-type flip-flop 20. The operation of this PLL demodulator generates a pulse width modulated signal stream so that the width of a positive output pulse from the PLL demodulator is a function of an input frequency. |
