发明名称 COMBINED CIRCUIT COMPOSED OF DIGITAL PHASE COMPARATOR WITH ZERO-DEBT BAND AND MINIMUM OFFSET AND CHARGE PUMP
摘要 PURPOSE: To eliminate the phase comparison dead band of a digital phase locked loop(PLL) by resetting a comparator through the function of a charge pump having both the functions of charging and discharging. CONSTITUTION: High-speed charging/discharging operation is performed inside a charge pump 15, a means for detecting the time when simultaneously executing both the functions of charging and discharging is provided, and the charge pump 15 is connected to a power source, the injection current source of a low- pass filter(LPF) and voltage controlled oscillator(VCO) coupling to be used for the PLL. Besides, since a digital phase detector 11 has a reset terminal for responding to the simultaneous charging/discharging operation of the charge pump 15, two kinds of charge pump operation appear before resetting is generated, and any delay element is not required. When increasing the frequency of a VCO, the up output of a phase comparator is made superior and the charge pump 15 injects a current into the LPF. When decreasing the frequency of the VCO, the down output of the phase comparator is made dominant, and the charge pump pulls a current out of the LPF. Thus, the dead band is removed.
申请公布号 JPS6469122(A) 申请公布日期 1989.03.15
申请号 JP19880204540 申请日期 1988.08.17
申请人 NATL SEMICONDUCTOR CORP <NS> 发明人 DEEBUITSUDO EI BAIAADO;GEERII DABURIYUU TEIITSU;KUREIGU EMU DEIBUISU
分类号 H03L7/085;G01R25/00;H03L7/089 主分类号 H03L7/085
代理机构 代理人
主权项
地址