发明名称
摘要 PURPOSE:To simplify processes, and to prevent the generation of a defective contact in an electrode contact section by providing a process forming an offset gate region and a pull-down resistor by implanting impurity ions of the same kind as pull-down resistor electrodes among these electrodes formed in the offset gate region and a reverse conduction type well region by an impurity of the same kind. CONSTITUTION:LOCOS Oxide films 22 are formed on an N type Si semiconductor substrate 21, and P well regions 25 and 26 are formed in regions surrounded by the oxide films 22. Polysilicon gate electrides 35 and 36 are formed through gate oxide films 33 and 34. The P well region 26 is removed, other sections are coated with a photo-resist, phosphorus ions, etc. are implanted, and the source region 31 and drain region 32 of an N channel type MOS transistor are formed in predetermined regions. The P well region 26 is coated with the photo-resist, boron ions in high concentration are implanted to the whole surfaces of other regions, and the electrodes 27, 28 of the pull-down resistors and the P type impurity concentration regions of the source region 29 and drain region 30 of a P channel type MOS transistor are formed.
申请公布号 JPH0115149(B2) 申请公布日期 1989.03.15
申请号 JP19820199677 申请日期 1982.11.16
申请人 MATSUSHITA ELECTRONICS CORP 发明人 NABETA YASUMASA
分类号 H01L21/8234;H01L21/8238;H01L27/088;H01L27/092;H01L29/78 主分类号 H01L21/8234
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