| 摘要 |
<p>A data processor is disclosed which includes a program memory storing a string of instruction, a program counter producing address data for designating a memory location of the program memory storing an instruction to be executed, an instruction decoder decoding the instruction read-out from the program memory and producing a first control signal, and an execution unit executing a first operation in response to the first control signal. The processor further includes a control signal generation circuit detecting that the address data from the program counter takes a specific content and producing a second control signal in response thereto. The processor thus executes a second operation responsive to the second control signal in parallel to the first operation.</p> |
