发明名称 |
Logic circuit connecting input and output signal leads |
摘要 |
This invention discloses a logic circuit including first, second and third transistors with the control terminals of two of those transistors being connected to the input signal lead, with the output signal lead being connected to one of the current handling terminals of one of those transistors, and with a load device connected to the respective current handling terminals of those two transistors and one of the voltage supply terminals.
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申请公布号 |
US4812683(A) |
申请公布日期 |
1989.03.14 |
申请号 |
US19870051984 |
申请日期 |
1987.05.19 |
申请人 |
GAZELLE MICROCIRCUITS, INC. |
发明人 |
FITZPATRICK, MARK E.;GRAHAM, ANDREW C. |
分类号 |
H03K19/0175;H03K3/0231;H03K3/3565;H03K19/0185;H03K19/094;H03K19/0944;H03K19/0952;(IPC1-7):H03K19/094 |
主分类号 |
H03K19/0175 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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