发明名称 Multiplier circuit suitable for obtaining a negative product of a multiplier and a multiplicand
摘要 A &upbar& P generator receives the multiplier data Y and produces the &upbar& P on the basis of the data Y2i, Y2i+1, and Y2i+2 of three continuous bits of the multiplier data Y (in which, it is defined that Pi=Y2i+Y2i+1-2xY2i+2, Pi=Y2i+Y2i+1-2xY2i+2' and Y0=0, and i=0, 1, . . . , n/2-1, and Yj is the bit data of the jth bit of the multiplier Y). A partial-product generator receives the &upbar& P from the &upbar& P generator and a multiplicand X, and obtains the partial products XxPi of the multiplicand X and the Pi. A partial-product adding circuit weights 22i to the partial products XxPi derived by the partial-product generator, and adds the resultant data, thereby producing the negative product (-XxY) of the multiplicand X and multiplier Y.
申请公布号 US4813008(A) 申请公布日期 1989.03.14
申请号 US19870028183 申请日期 1987.03.19
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SHIGEHARA, HIROSHI;SHIRAISHI, MIKIO;WATANABE, YASUHIRO;SUGI, NOBUO
分类号 G06F7/533;G06F7/52;G06F7/53;(IPC1-7):G06F7/52 主分类号 G06F7/533
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