| 摘要 |
<p>PURPOSE:To reduce the power consumption by holding a potential at an output terminal to a low potential when no logic circuit is in use so as to decrease the current lowing to a lead resistor. CONSTITUTION:The logic circuit consists of a NAND circuit 3, a load resistor R, a power supply -V, and an effective time control means 2. An output 12 of the effective time control means 2 is connected to on input of the NAND circuit 3 and the other input of the NAND circuit 3 is an input terminal I. The effective time control means 2 consists of a flip-flop or the like and holds the output 12 to logical '1' (low potential) in response to a trigger signal from a processing unit or the like (not shown) given to the input terminal 11. Thus, when no logic circuit is used, a logical 1 (low potential) always appears at the output terminal O of the NAND circuit 3 and the current flowing to the load resistor R is reduced.</p> |
