| 摘要 |
PURPOSE:To ease an interface between a central processing unit and a surrounding circuit, whose operating forms are mutually different, by inserting the necessary number of wait cycles based on the instruction of a synchronizing control means to supervize the phases of reference operating clock signals to be mutually different. CONSTITUTION:A central processing unit 1 inserts the necessary number of the wait cycles according to an access starting timing to surrounding circuits 2 and 3, which are operated based on the reference operating clock signal to be different from the central processing unit 1, based on the instruction of a synchronizing control means 8 to supervize the phases of the mutually different reference operating clock signals. Then, a read and write timing is synchronized between the central processing unit 1 and the surrounding circuits 2 and 3. Thus, the interface can be easily obtained between the central processing unit and the surrounding circuits 2 and 3 whose operating forms are mutually different. |
