| 摘要 |
<p>PURPOSE: To make the operation speed fast and synchronize a high-speed integrated circuit by constituting reduced instruction set computer processors as plural integrated circuits. CONSTITUTION: The computer system includes a high-speed reduced instruction set computer processor 12. At the time of its operation, the page of an instruction in a main memory 28 is transferred to a cache 18 and supplied to a processor 12 through a bus 14. When the processor seek to write or read data to or read out of an address in a specific page in an address space, the page is transmitted from the memory 28 to the cache 22. A controller 30 monitors an address on buses 14 and 24 and interrupts the processor 12 unless the address is present in the current page of one of memories 16-22. Then, when the processor 12 restarts memory access, an arithmetic processor 34 performs high-speed arithmetic operation under the control of the processor 12.</p> |
