Bit-serial comparator

摘要

Method and device to implement bit-serial comparators with the ability to be reset (R), for comparison of two binary-coded input variables (A, B), with three different comparator states (A < B, A = B, A > B). The bit-serial comparator contains two memory elements, each with four 2-bit wide memory states (0/0, 0/1, 1/0, 1/1). Of the (2<2>)! available possible assignments of different memory states to different comparator states, (2<2>) optimal possible assignments are selected, by assigning a free memory state, which is not required for coding the various comparator states, to a comparator state which is used for control. <IMAGE>