发明名称 SHIFT COUNT REGISTER CIRCUIT
摘要 PURPOSE:To provide two functions to one circuit by bringing J, K terminals of a JK flip-flop to all high level to act it as a flip-flop and bringing the levels of the J, K terminals opposedly to each other to cause D-FF operation thereby forming a shift counter. CONSTITUTION:When a load signal LD reaches an L level, the input to data terminals A to D causes a hexadecimal number 'A' at terminals QA to QD. With the load signal LD at an H level, a count enable signal CE at an H level and a switching signal C/S at an L level, then the count is started at the leading of a clock signal CLOCK. When the switching signal C/S reaches an H level, data of a serial input signal SI is loaded (H level) to the terminal QA at the leading of the clock signal at a location (d) and the shift is started at the leading of the clock signal.
申请公布号 JPS6461118(A) 申请公布日期 1989.03.08
申请号 JP19870216393 申请日期 1987.09.01
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NAKAYAMA YOSHITERU
分类号 G11C19/00;H03K21/00;H03K23/50 主分类号 G11C19/00
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