| 摘要 |
<p>An arithmetic unit (1) conducts a series of comparison/logic operations and outputs the result as non-exceptional status signal as well as the presence of an error as exceptional status signal. The status signals are decoded (2) and selected (4) under the control of a micro program control unit (5). An error memory (3) receives the decoded output (D2) of the exceptional status signal and stores information about the presence of an error during the series of operations. This enables the confirmation of errors at the completion of the operations.</p> |
