发明名称 ON-CHIP SUBSTRATE VOLTAGE GENERATION CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To increase the capacity of a substrate voltage generation circuit and to increase the operation margin of an integrated circuit by detecting, when a power source voltage increases, the voltage by a level detecting circuit, and sequentially operating a negative voltage generation circuit with an operation control terminal. CONSTITUTION:A substrate voltage generation circuit is composed of 2 level detection circuits D1, D2 and 3 negative voltage generation circuits G0, G1, G2. If a power source voltage VCC is the detection level VC1 or of the detection circuit D1, below, only the generation circuit G0 operates, but the generation circuits G1, G2 do not operate. In case of VC1<=VCC<=VC2, the generation circuits G0, G1 operate, and in case of VCC>=VC2, all the generation circuits G0, G1, G2 operate. Then, the capacity of the substrate voltage generation circuit is enhanced corresponding to the increase in the substrate current due to the enhancement of the voltage VCC. Thus, the operation margin of an integrated circuit is increased.
申请公布号 JPS6461045(A) 申请公布日期 1989.03.08
申请号 JP19870219450 申请日期 1987.09.01
申请人 NEC CORP 发明人 TAKESHIMA TOSHIO
分类号 H01L27/04;G11C11/407;H01L21/822;H01L27/02 主分类号 H01L27/04
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