发明名称 SOLID ERROR DETECTOR OF IC MEMORY
摘要 PURPOSE:To decrease the number of replacements of a printed board, by discriminating an intermittent error from a solid error. CONSTITUTION:A 1-bit error is outputted from an ECC check circuit 5 of an IC memory circuit 1 and then detected by a processor 2. This detection is transmitted to a controller 8 via a line 11. The error corrected data read out a memory 3 is held at a register 7. At the same time, a signal line 13 is checked, and the writing is carried out again to the same address of the register 7 when a 1-bit error is generated. These written contents are read out to give the second check to the line 13 to decide 8 the presence or absence of a 1-bit error. When a 1-bit error is detected again, a signal is applied to the line 11 to deliver an alarm to outside. In such a way, an intermittent error is discriminated from a solid error for the memory 3.
申请公布号 JPS5936399(A) 申请公布日期 1984.02.28
申请号 JP19830067472 申请日期 1983.04.15
申请人 HITACHI SEISAKUSHO KK 发明人 TAKAMATSU RIYOUICHI;KATOU TAKESHI
分类号 G06F11/10;G06F12/16 主分类号 G06F11/10
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