发明名称 Signal processing circuit
摘要 A signal processing circuit comprises a constant value generating circuit for generating a constant value ( alpha i) corresponding to a delay time (di) for an input signal (Vi(t)); an adding/subtracting circuit for alternately adding the constant value to the input signal and subtracting the constant value from the input signal for every half period of the input signal; and an amplitude correcting circuit for correcting an amplitude of an output signal of the adding/subtracting circuit for every half period of the input signal so that a delayed output signal (Vo(t)) having a waveform corresponding to a waveform of the input signal is produced.
申请公布号 US4811260(A) 申请公布日期 1989.03.07
申请号 US19870119451 申请日期 1987.11.10
申请人 FUJITSU LIMITED 发明人 ABE, MASATO;ASAMI, FUMITAKA
分类号 H03H17/00;(IPC1-7):G06F7/38 主分类号 H03H17/00
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