发明名称 |
Stack frame cache on a microprocessor chip |
摘要 |
A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.
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申请公布号 |
US4811208(A) |
申请公布日期 |
1989.03.07 |
申请号 |
US19860863878 |
申请日期 |
1986.05.16 |
申请人 |
INTEL CORPORATION |
发明人 |
MYERS, GLENFORD J.;LAI, KONRAD;IMEL, MICHAEL T.;HINTON, GLENN;RICHES, ROBERT |
分类号 |
G06F9/42;G06F9/30;G06F9/40;G06F9/46;G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F9/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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