发明名称 STEREOSCOPIC SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To easily cope with the change of input levels and to more emphasize the directional feeling of a reproduced sound by 1/2nd-power-compressing inputted channel signals in accordance with their levels, after that, obtaining an arithmetic mean, further, 2nd-power-expanding it and reproducing it in an intermediate position. CONSTITUTION:The titled circuit is equipped with a first and a second level compressing circuits 5L and 5R to compress a first and a second channel signals L and R in accordance with their levels V1 and V2 into a V1<1/2>-fold one and a V2<1/2>-fold one respectively, arithmetic mean circuits 6 and 7 to obtain the arithmetic mean of the respective output signals of the first and the second level compressing circuits 5L and 5R, and a level expanding circuit 8 to expand the output signal of the arithmetic mean circuits 6 and 7 in accordance with its level V3 into a V -fold one. The output signal of the level expanding circuit 8 is a third signal C which should be reproduced in the middle position of the respective reproducing positions of the first and the second channel signals L and R. Thus, deflections can be reduced and the directional feeling of the reproduced sound can be emphasized. Since the titled circuit is a self operation type, an equal effect can be obtained to any input levels.
申请公布号 JPS6460200(A) 申请公布日期 1989.03.07
申请号 JP19870217521 申请日期 1987.08.31
申请人 YAMAHA CORP 发明人 FUJITA SHINICHI
分类号 H04S3/00;H04S5/02 主分类号 H04S3/00
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