| 摘要 |
A multiport RAM register file adapted for flowing data directly from an input port to an output port and for simultaneously writing to a location in the register file. In addition to the RAM register, the apparatus includes (1) a first set of multiplexers between the input ports and the RAM, (2) a second set of multiplexers between the output of the RAM and the output ports and (3) logic for controlling the multiplexers and writing to the RAM. The input multiplexers are controlled by flow-through address comparators; the output multiplexers are controlled by read address comparators. The data at any input port of the register file may be written to any of the RAM data bit buses by selecting the input multiplexer appropriately. Because the bit buses are being driven, this data simultaneously may be passed to the RAM output just as if the RAM were being read-i.e., as a flow-through. Further, if the RAM address lines are activated concurrently, this data can be written to a selected cell while it is flowing-through to the output port. The output multiplexers feed the data from the bit lines to a selected output port (or ports).
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