| 摘要 |
PURPOSE:To attain improvement in yield and operational speed concurrently by simplification of a manufacturing process of a BiCMOS integrated circuit by a method wherein a polycrystalline emitter electrode and a polycrystalline gate electrode are formed on an emitter contact hole and a gate insulating film provided on a PMOS forming region and an NMOS forming region respectively. CONSTITUTION:A gate insulating film 7 formed on a P-type base region 10 is removed through a usual resist method so as to expose a silicon surface, an emitter contact hole is opened, and then a polycrystalline silicon layer 11 is made to be deposited through a vacuum CVD method so as to be 300nm in thickness. Next, a polycrystalline emitter electrode 14 and a polycrystalline gate electrodes 12-1 and 12-2 are processed to be formed, As ions are selectively implanted with energy of 50keV in dose of 1.0X10<16>cm<-2> ion and annealing is adequately performed, whereby an emitter region 15 and a collector contact region 16 of an NPN bipolar transistor and a source and a drain regions 17-1 and 17-2 of an NMOSFET can be formed. |
