| 摘要 |
<p>PURPOSE:To prevent the malfunction of a memory cell due to a voltage stress by impressing a prescribed straight polarity voltage into the erasing gate of the memory cell at the time of writing data. CONSTITUTION:The erasing gates of memory cells M1-M4 constituting a memory cell array are commonly connected to an erasing line EL, and a reference voltage is impressed to a source. In the memory cell array with such a constitution, for example, in order to write a data '0' into the cell M1, the high voltage of +10V is impressed to a data line DL1, and the high voltage of +21V is impressed to a word line ML1. At such a time, the other data line DL1 and word line WL1 are set at 0V respectively. In addition, a prescribed voltage VEG is impressed to the erasing line EL. In such a condition, though the nonselective memory with the largest voltage stress is the cell M2, it is drastically improved compared with the case of setting the voltage VEG at 0V. thus, the generation of the erroneous writing in the cell M2 can be suppressed.</p> |
